Various embodiments of the present disclosure generally relate to semiconductor devices and methods of fabricating the same and, more particularly, to semiconductor devices having double-layered metal contacts and methods of fabricating the same.
Semiconductor memory devices may include dynamic random access memory (DRAM) devices as typical volatile memory devices, and the DRAM devices may include cell capacitors to store data. In order to fabricate high density DRAM devices, memory cells including the cell capacitors must be scaled down in size to the sub-micrometer range. This causes reduction of cell capacitor area, resulting in reduction of cell capacitance. In this case, the reduction of the cell capacitance may lead to a decrease in refresh cycle time of the DRAM devices and may result in an increase of soft error rates (SER) which are due to alpha particles. That is, the reduction of the cell capacitance may lead to the decrease of a sensing margin of the DRAM devices and malfunction of the DRAM devices. Meanwhile, a parasitic capacitance, for example, a bit line capacitance should be reduced to obtain a fast operation speed of the DRAM devices. Accordingly, in order to realize high performance DRAM devices with high integration density, the cell capacitance should be increased whereas the parasitic capacitance should be reduced.
As the DRAM devices become more highly integrated, a design rule (e.g., a minimum feature size) has been abruptly reduced. Thus, a height of the cell capacitors should be increased to obtain a sufficient cell capacitance for realizing high performance DRAM devices. However, in the event that the height of the cell capacitors increases, a step height between a cell array region and a peripheral circuit region may also increase. In such a case, burden on an etch process for forming a plate node on the cell array region may be increased. That is, a process margin of the etch process for forming the plate node may be reduced. Further, as the design rule of the DRAM devices becomes reduced, a pitch size of line patterns formed in the peripheral circuit region may also be reduced. Thus, it may be difficult to accurately form the line patterns in the peripheral circuit region using a single patterning technology. Accordingly, a double patterning technology has been proposed to form the fine line patterns in the peripheral circuit region.
Moreover, as the height of the cell capacitors become more increased, heights of metal contact plugs for connecting transistors or the cell capacitors to metal lines may also be increased. The metal contact plugs may be formed in metal contact holes. Thus, depths of the metal contact holes may also be increased. If the depths of the metal contact holes increase, a probability of electrical shortages between the adjacent metal contact plugs may be increased. This is because the metal contact holes are formed to have sloped sidewalls. For example, the metal contact holes may be formed to have positive sloped sidewalls because of the nature of the etch process for forming the metal contact holes. In particular, when a cleaning process is applied to a substrate including the metal contact holes, the metal contact holes may be enlarged to more increase the probability of the electrical shortages between the adjacent metal contact plugs. Accordingly, distances between metal contact holes should be increased to prevent the electrical shortages between the adjacent metal contact plugs. However, in such a case, the integration density of the DRAM devices may be degraded.